Logic networks, such as flip-flops, are in general use, especially as logic-state storage elements in integrated circuits of the digital type.
A logic state of "1" is usually associated with a signal at a high level, i.e., "logic high", and a logic state of "0" with a signal at a low level, i.e., "logic low".
A standard SR flip-flop is an asynchronous sequential network having two inputs, S and R, and an output, Q.
When to the input S is applied a Set signal, typically at a logic high (usually a pulse of short duration), the flip-flop outputs a signal whose logic level remains high until a Reset signal at a logic high level is applied to the input R.
It is important to observe that the simultaneous application of signals at a logic high to both Set and Reset terminals is not envisaged by existing SR flip-flops.
Thus, the output Q of an SR flip-flop is responsive to the level of the input signals.
But this feature may introduce problems in certain applications. In fact, the way the Set and Reset signals follow each other may be inconsistent, and their time duration may be undefined, so that there may be time intervals when to both inputs are applied signals that are logic high. Such an application often makes the flip-flop operation erratic, resulting in faulty operation of the device in which it is connected.
A prior attempted solution to this drawback has been to make the Set-Reset flip-flop responsive, rather than to the level of the input signal, to the signal leading or trailing edges--i.e., the signal edges--present in the signal waveform.
The SR flip-flop responsive to signal edges is a logic network (finite state sequential machine) having two inputs (S and R) and an output (Q). When a useful signal edge appears at the input S, a logic "1" is placed on the output Q, and when a useful signal edge appears at the input R, a logic "0" is placed on the output Q. The flip-flop state (and, hence, the state of the output Q) does not change before a useful edge appears at the opposite input from the one that altered it. The useful edges for the two inputs may differ from each other, but for each of the inputs, there can be but one useful edge: either the leading (positive-going) edge or the trailing (negative-going) edge.
Throughout the ensuing description, it should be understood that a high logic level represents a "1", and a low logic level a "0". As for the polarity of the useful edges, the positive polarity will be considered for both inputs.
In the prior art, it has been common practice to make an SR flip-flop responsive to signal edges by providing an SR flip-flop with a shunter or a monostable on its inputs.
In either case, however, the system operation is tied to the time constants of the shunter or the monostable as concerns the acquisition times of the flip-flop. Often, these time constants cannot be made very small, and thus they will slow down the dynamic range (penalizing in particular the minimum time between two useful edges) of the system accordingly.
Furthermore, the integration area occupied by such structures placed at the inputs is far from negligible compared to the size of the flip-flop, while performance becomes contingent both on variations in the integrating process and on such additional parameters as temperature or supply voltage.
An example of an SR flip-flop responsive to signal edges which uses monostables on its inputs is disclosed in U.S. Pat. No. 3,976,949 granted to Motorola Inc. on Aug. 24, 1976, which is incorporated by reference herein.